? semiconductor components industries, llc, 2002 april, 2002 rev. 2 1 publication order number: mc100lve310/d mc100lve310 3.3vecl 2:8 differential fanout buffer the mc100lve310 is a low voltage, low skew 2:8 dif ferential ecl fanout buffer designed with clock distribution in mind. the device features fully differential clock paths to minimize both device and system skew. the lve310 offers two selectable clock inputs to allow for redundant or test clocks to be incorporated into the system clock trees. to ensure that the tight skew specification is met it is necessary that both sides of the differential output are terminated into 50 w , even if only one side is being used. in most applications all eight differential pairs will be used and therefore terminated. in the case where fewer than eight pairs are used it is necessary to terminate at least the output pairs adjacent to the output pair being used in order to maintain minimum skew. failure to follow this guideline will result in small degradations of propagation delay (on the order of 1020 ps) of the outputs being used, while not catastrophic to most designs this will result in an increase in skew. note that the package corners isolate outputs from one another such that the guideline expressed above holds only for outputs on the same side of the package. the mc100lve310, as with most ecl devices, can be operated from a positive v cc supply in lvpecl mode. this allows the lve310 to be used for high performance clock distribution in +3.3 v systems. designers can take advantage of the lve310's performance to distribute low skew clocks across the backplane or the board. in a pecl environment series or thevenin line terminations are typically used as they require no additional power supplies, if parallel termination is desired a terminating voltage of v cc 2.0 v will need to be provided. for more information on using pecl, designers should refer to application note an1406/d. the v bb pin, an internally generated voltage supply, is available to this device only. for single-ended input conditions, the unused differential input is connected to v bb as a switching reference voltage. v bb may also rebias ac coupled inputs. when used, decouple v bb and v cc via a 0.01 f capacitor and limit current sourcing or sinking to 0.5 ma. when not used, v bb should be left open. ? 200 ps parttopart skew ? 50 ps outputtooutput skew ? the 100 series contains temperature compensation ? esd protection: >2 kv hbm, >200 v mm ? pecl mode operating range: v cc = 3.0 v to 3.8 v with v ee = 0 v ? necl mode operating range:v cc = 0 v with v ee = 3.0 v to 3.8 v ? internal input pulldown resistors ? q output will default low with all inputs open or at v ee ? meets or exceeds jedec spec eia/jesd78 ic latchup test ? moisture sensitivity level 1 for additional information, see application note and8003/d ? flammability rating: ul94 code v0 @ 1/8o, oxygen index 28 to 34 ? transistor count = 212 devices device package shipping ordering information mc100lve310fn plcc28 37 units/rail marking diagram a = assembly location wl = wafer lot yy = year ww = work week plcc28 fn suffix case 776 mc100lve310fnr2 plcc28 500 units/reel mc100lve310 awlyyww 128 http://onsemi.com
mc100lve310 http://onsemi.com 2 1 56 7891011 25 24 23 22 21 20 19 26 27 28 2 3 4 18 17 16 15 14 13 12 v ee clk_sel clka v cc clka v bb clkb q3 q3 q4 v cco q4 q5 q5 pinout: 28lead plcc (top view) q0 q0 q1 v cco q1 q2 q2 clkb q7 q6 nc v cco q7 q6 logic symbol q0 q0 q1 q1 q2 q2 q3 q3 v bb clka clka q4 q4 q5 q5 q6 q6 q7 q7 clkb clkb clk_sel pin description function ecl differential input clocks ecl differential outputs ecl input clock select reference voltage output positive supply negative supply no connect pin clka, clka ; ,clkb clkb q0:7, q0:7 clk_sel v bb v cc , v cco v ee nc input clock clka selected clkb selected clk_sel l h warning: all v cc , v cco , and v ee pins must be externally connected to power supply to guarantee proper operation. logic diagram and pinout assignment maximum ratings (note 1) symbol parameter condition 1 condition 2 rating units v cc pecl mode power supply v ee = 0 v 8 to 0 v v ee necl mode power supply v cc = 0 v 8 to 0 v v i pecl mode input voltage v ee = 0 v v i v cc 6 to 0 v necl mode input voltage v cc = 0 v cc v i v ee 6 to 0 v i out output current continuous surge 50 100 ma ma i bb v bb sink/source 0.5 ma ta operating temperature range 40 to +85 c t stg storage temperature range 65 to +150 c q ja thermal resistance (junction to ambient) 0 lfpm 500 lfpm 28 plcc 28 plcc 63.5 43.5 c/w c/w q jc thermal resistance (junction to case) std bd 28 plcc 22 to 26 5% c/w t sol wave solder <2 to 3 sec @ 248 c 265 c 1. maximum ratings are those values beyond which device damage may occur.
mc100lve310 http://onsemi.com 3 lvpecl dc characteristics v cc = 3.3 v; v ee = 0.0 v (note 1) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 55 60 55 60 65 70 ma v oh output high voltage (note 2) 2215 2295 2420 2275 2345 2420 2275 2345 2420 mv v ol output low voltage (note 2) 1470 1605 1745 1490 1595 1680 1490 1595 1680 mv v ih input high voltage (single ended) 2135 2420 2135 2420 2135 2420 mv v il input low voltage (single ended) 1490 1825 1490 1825 1490 1825 mv v bb output voltage reference 1.92 2.04 1.92 2.04 1.92 2.04 v v ihcmr input high voltage common mode range (differential) (note 3) 1.8 2.9 1.8 2.9 1.8 2.9 v i ih input high current 150 150 150 m a i il input low current 0.5 0.5 0.5 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary 0.3 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts. 3. v ihcmr min varies 1:1 with v ee , max varies 1:1 with v cc . v ihcmr is defined as the range within which the v ih level may vary, with the device still meeting the propagation delay specification. the v il level must be such that the peak to peak voltage is less than 1.0 v and greater than or equal to v pp (min). lvnecl dc characteristics v cc = 0.0 v; v ee = 3.3 v (note 1) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 55 60 55 60 65 70 ma v oh output high voltage (note 2) 1085 1005 880 1025 955 880 1025 955 880 mv v ol output low voltage (note 2) 1830 1695 1555 1810 1705 1620 1810 1705 1620 mv v ih input high voltage (single ended) 1165 880 1165 880 1165 880 mv v il input low voltage (single ended) 1810 1475 1810 1475 1810 1475 mv v bb output voltage reference 1.38 1.26 1.38 1.26 1.38 1.26 v v ihcmr input high voltage common mode range (differential) (note 3) 1.5 0.4 1.5 0.4 1.5 0.4 v i ih input high current 150 150 150 m a i il input low current 0.5 0.5 0.5 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary 0.3 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts. 3. v ihcmr min varies 1:1 with v ee , max varies 1:1 with v cc . v ihcmr is defined as the range within which the v ih level may vary, with the device still meeting the propagation delay specification. the v il level must be such that the peak to peak voltage is less than 1.0 v and greater than or equal to v pp (min).
mc100lve310 http://onsemi.com 4 ac characteristics v cc = 3.3 v; v ee = 0.0 v or v cc = 0.0 v; v ee = 3.3 v (note 1.) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f max maximum toggle frequency tbd tbd tbd ghz t plh t phl propagation delay to output in (differential) (note 2.) in (singleended) (note 3.) 525 500 725 750 550 550 750 800 575 600 775 850 ps t skew withindevice skew (note 4.) parttopart skew (differential) 75 250 50 200 50 200 ps t jitter cycletocycle jitter tbd tbd tbd ps v pp input swing (note 5.) 500 1000 500 1000 500 1000 mv t r /t f output rise/fall time (20%80%) 200 600 200 600 200 600 ps 1. v ee can vary 0.3 v. 2. the differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the differential output signals. 3. the single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the out put signal. 4. the withindevice skew is defined as the worst case difference between any two similar delay paths within a single device. 5. v pp (min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. the v pp (min) is ac limited for the lve310 as a differential input as low as 50 mv will still produce full ecl levels at the output. figure 1. typical termination for output driver and device evaluation (see application note and8020 termination of ecl logic devices.) driver device receiver device qd 50 50 v tt q d v tt = v cc 2.0 v resource reference of application notes an1404 eclinps circuit performance at nonstandard v ih levels an1405 ecl clock distribution techniques an1406 designing with pecl (ecl at +5.0 v) an1503 eclinps i/o spice modeling kit an1504 metastability and the eclinps family an1560 low voltage eclinps spice modeling kit an1568 interfacing between lvds and ecl an1596 eclinps lite translator elt family spice i/o model kit an1650 using wireor ties in eclinps designs an1672 the ecl translator guide and8001 odd number counters design and8002 marking and date codes and8020 termination of ecl logic devices
mc100lve310 http://onsemi.com 5 package dimensions plcc28 fn suffix plastic plcc package case 77602 issue e n m l v w d d y brk 28 1 view s s l-m s 0.010 (0.250) n s t s l-m m 0.007 (0.180) n s t 0.004 (0.100) g1 g j c z r e a seating plane s l-m m 0.007 (0.180) n s t t b s l-m s 0.010 (0.250) n s t s l-m m 0.007 (0.180) n s t u s l-m m 0.007 (0.180) n s t z g1 x view dd s l-m m 0.007 (0.180) n s t k1 view s h k f s l-m m 0.007 (0.180) n s t notes: 1. datums -l-, -m-, and -n- determined where top of lead shoulder exits plastic body at mold parting line. 2. dimension g1, true position to be measured at datum -t-, seating plane. 3. dimensions r and u do not include mold flash. allowable mold flash is 0.010 (0.250) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. dimension h does not include dambar protrusion or intrusion. the dambar protrusion(s) shall not cause the h dimension to be greater than 0.037 (0.940). the dambar intrusion(s) shall not cause the h dimension to be smaller than 0.025 (0.635). dim min max min max millimeters inches a 0.485 0.495 12.32 12.57 b 0.485 0.495 12.32 12.57 c 0.165 0.180 4.20 4.57 e 0.090 0.110 2.29 2.79 f 0.013 0.019 0.33 0.48 g 0.050 bsc 1.27 bsc h 0.026 0.032 0.66 0.81 j 0.020 --- 0.51 --- k 0.025 --- 0.64 --- r 0.450 0.456 11.43 11.58 u 0.450 0.456 11.43 11.58 v 0.042 0.048 1.07 1.21 w 0.042 0.048 1.07 1.21 x 0.042 0.056 1.07 1.42 y --- 0.020 --- 0.50 z 2 10 2 10 g1 0.410 0.430 10.42 10.92 k1 0.040 --- 1.02 ---
mc100lve310 http://onsemi.com 6 notes
mc100lve310 http://onsemi.com 7 notes
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